Although make is part of the gnu toolset, its use is not restricted to compile a c++ program. make can be used to do various kinds of work.

Here is my notes on makefile for my future self. I find it of great help to keep these notes handy. For example, I often come back for this one

Macro

  • Define macro(variable, but it’s called macro in makefile) with equal sign, multiple values can be assigned to one macro. use macro in the form of $(A)
A = a b c
$(A)

Rules

  • The structure of a rule
%.o: $(DEPS)
	$(CC) -c -o $@ $< $(CFLAGS)
  • %.o: target file
  • $(DEPS): file dependency (to generate target)
  • \tab+command: usual linux commands

My notes:

  • Type make will run the first rule in a Makefile.

  • Special rule: .PHONY: clean tells make that clean is not a file. Always execute commands under the clean rule, even if there’s a clean file in the working directory.

  • Automatic variables

    • $@ target of the rule
    • $< first prerequisite
    • $^ all prerequisite

  • Sublime will transform tab to 4 spaces, turn that off for makefile

  • @ before a command will prevent printing the command before executing.

  • % for quoting.

Resources

gnu make manual

A Simple Makefile Tutorial

An interesting SO question of makefile use case